1. Field of the Invention
The present invention relates to a solid state image pickup device suitable for use as an automatic focussing solid state image pickup device with a photometry function, particularly as a compact camera automatic focussing sensor of a phase difference detection and external photometry type.
2. Related Background Art
A range finding (automatic focussing, AF) sensor with a photometry (automatic exposure, AE) function for a conventional lens-shutter compact camera has been realized as a solid state image pickup device as disclosed, for example, in U.S. Pat. No. 5,302,997. A schematic plan layout of this solid state image pickup device is shown in FIG. 11. Referring to FIG. 11, an AE sensor array 30 is constituted of an AE center segment 32, AE inner segments 34A, 34B, 34C and 34D and AE outer segments 36A, 36B, 36C and 36D. The solid state image pickup device has also AF sensor arrays (linear sensor arrays) 40 and 42 constituted of pixels 441-n and 461-n, respectively. The AE sensor array 30 and AF sensor arrays 40 and 42 are formed on a silicon semiconductor substrate 50. The AE region has a height H and a width W. The baseline length is represented by D.
Two AF linear sensor arrays 40 and 42 are used for performing photometry through phase difference detection. An AF sensitivity representative of a range finding precision can be given by:AF sensitivity=D×f/P where P is a pixel pitch and f is a focal length of an AF lens. A solid state image pickup device having the AF sensitivity of about 5000 is presently available. If a pixel pitch is about 10 μm and a lens focal length is about several mm, then the baseline length is 5 mm to 8 mm. There is, therefore, an invalid region between the linear sensors 40 and 42. However, the AE sensor 30 is formed in this invalid region to effectively use the area of the semiconductor substrate. By integrating the AE sensor 30 and AF sensors 40 and 42 on one chip, a compact and inexpensive camera can be realized.
FIG. 12 is a cross sectional view taken along line 12-12 shown in FIG. 11. For the purposes of simplicity, the number of photodiodes in the AF sensor region and AE sensor regions drawn in FIG. 12 is reduced. Referring to FIG. 12, reference numeral 51 represents an n-type Si substrate, 52 represents an n-type epitaxial layer, 53 represents a p-type well (PWL), 54 represents an n+-type impurity layer, 55 represents a thin oxide film, 56 represents a thick oxide film (locally oxidized silicon) as an element separation region, 57 represents an aluminum (Al) wiring pattern and 58 represents an interlayer insulating film. PWL 53 and n+-type impurity layer 54 constitute a photodiode. As light becomes incident upon the photodiodes in the AE and AF sensor regions, pairs of electrons and holes are generated in the semiconductor through photoelectric conversion. Holes represented by black circles are drained to the ground potential (GND) via PWL 53, whereas electrons represented by white circles are absorbed in the n+-type impurity layers 54 in the AE and AF sensor regions. AE and AF signals are generated by electrons collected in the n+-type impurity layers 54 in the AE and AF sensor regions. However, since the AE and AF sensor regions are formed near each other, large electric and optical crosstalks occur between AE and AF photodiodes in the AE and AF regions.
Problems associated with a conventional solid state image pickup device will be described with reference to FIG. 12. Some of electrons represented by white circles and generated under AE photodiodes in the AE region diffuse into adjacent AF photodiodes in the AF region as indicated by an arrow Df1. Some of electrons represented by white circles and generated under AF photodiodes in the AF region diffuse into adjacent AE photodiodes in the AE region as indicated by an arrow Df2. Stray light indicated by a straight arrow and incident upon photodiodes results in crosstalks. In addition to such crosstalks generated optically, there are crosstalks generated electrically via parasitic capacitance Cp between wiring lines.
If the densities of wiring patterns are irregular in the layout of a solid state image pickup device, there occurs a problem of a lowered precision of a chemical mechanical polishing (CMP) planarization process among CMOS manufacture processes. If the densities of wiring patterns are uniform, the planarized surface is uniform, whereas if the densities of wiring patterns are irregular, the planarized surface is irregular. This is because the polishing speed changes with the presence/absence of wiring patterns under the interlayer insulating film. Irregularity becomes large if there is a region without wiring patterns, among others a region without wiring pattern over a length of about 100 μm. Generally, the positions of AE and AF sensors of an AE/AF solid state image pickup device are determined by an optical system. There is, therefore, the tendency that the densities of wiring patterns become irregular depending upon the chip position and a planarization precision becomes poor.